Crystal Oscillator Design

Ever wonder what goes in to the design of a crystal oscillator? We’ll examine the operational theory of crystal oscillators, and design a discrete Pierce crystal oscillator suitable for use as a local oscillator in an HF receiver.

My discrete Pierce oscillator design tool can be found here; references and additional reading are listed below!

Description Reference
Oscillator circuit design and crystal loaded Q analysis Crystal Oscillator Circuits, Robert J. Matthys, Chapters 5.8, 6.1, 10.9
Pierce oscillator negative resistance and gain margins Understanding Quartz Crystals and Oscillators, Ramon M. Cerda, Chapters 9.2, 9.4
Pierce oscillator crystal drive level equations Intel application note AP-155 (Oscillators for Microcontrollers), Appendix A

21 thoughts on “Crystal Oscillator Design

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  5. Hi Craig,

    Nice video! Nice tool.

    I’m designing a 13.560 MHz oscillator, trying to use your tool. I’m having trouble and wondering what I’m doing wrong. Hopefully it’s something obvious.

    I’m wondering if you have time to comment.

    a) Trying to use a 2N2222A for the transistor. I’m assuming it is very similar to the 2N3904 you mentioned in the video. (Q: Is this a poor choice? Do you have suggestions for something better?)

    b) I chose bias resistor values very similar to those you used. However, I want to use a 5V VCC so I changed R1 to 27000, but left R4 at 3900.

    c) I’ll list all the parameters I selected: VCC:5, R1:27000, R2:27000, R3:1500, R4:3900, Q1:300, C1:220, C2:100, C3:15, ESR:60, Freq:13.56, C0:7, VPP:6

    These give: Load Capacitance:15.31 (Q: CL of my crystal is 20pf. Is this close enough?), Drive:2.33 uW (Q: Is this too low?)
    Loaded Q:92.22% (Q: Is this high enough?)
    Gain Margin:4.22 (Q: Is this enough gain?)

    I carefully prototyped the circuit (dead-bug), but it doesn’t oscillate.

    It would be awesome if you could make some suggestions!

    Thanks in advance!

    Bruce

    • FYI – I changed C3:22 and C2:120. This now gives CL 20.14, drive:8.11, Q:92.04%, Gain Margin: 3.51. However, it still doesn’t oscillate.

    • Hi Bruce!

      Q: Trying to use a 2N2222A for the transistor. Is this a poor choice? Do you have suggestions for something better?

      Generally a 2N3904 or 2N2222 is more than adequate for most oscillator applications, especially at the frequencies you’re working at.

      Q: Load Capacitance:15.31. CL of my crystal is 20pf. Is this close enough?

      The crystal will operate slightly off frequency, but this should not prevent oscillation altogether. Note that the calculated CL is only approximate anyway, as it will vary due to changes in capacitor tolerance, parasitic capacitance, etc.

      Q: Drive:2.33 uW. Is this too low?

      This is a bit on the low side, but I think this should be fine. It really depends on the crystal, but generally you don’t want to go too far below 1uW, as you can have problems with “drive level dependance” if the drive level is too high or too low.

      Q: Loaded Q is 92.22%. Is this high enough?

      That’s actually a very excellent loaded Q! For many applications, any loaded Q (for a quartz crystal) above 50% is probably fine, unless you have a special need for very good phase noise.

      Q: Gain Margin is 4.22. Is this enough gain?

      A gain margin of 4 is sufficient, though I’ve found often I can go lower. For reliability though, I’d keep it at or above 3.

      The problem I see is with the transistor biasing. Your base voltage is going to be around 2.5V, while the collector voltage is less than 1V! The transistor is not biased in its linear region, which is a requirement for oscillation.

      I haven’t tried building it myself, but changing R4 from 3900 ohms to 1200 ohms should put the transistor in a linear state. Although it will drop the loaded Q, it should still be above 70-80%, and I’d expect the circuit to oscillate.

  6. Hi Craig,

    Excellent explanation! It helps me a lot. I’m new with the oscillators and I don’t understand why in the final circuit you dont have the capacitance (before the input in the transistor ‘base’ and after the output in the transistor ‘collector’) for the decoupling AC – DC.

    Thanks in advance,

    John

    • Often you do AC couple the output, although not always; the collector’s DC bias is sometimes used to bias the next amplifier stage. In this case, I was probing the collector output with an AC coupled ‘scope probe, which provided the AC coupling.

      The crystal itself provides the AC coupling to the base of the transistor (the crystal is literally a rock with two electrodes on either side of it!).

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  8. Hey, this is Wayne. I’m trying to build one crystal oscillator with oscillating frequency at 50MHz. I’m just wondering is it possible that I replace the transistor with a op amp. Can I just build a inverting op amp to replace the transistor. Thank you

  9. Hey this is Wayne. Im thinking is it possible that i replace the transistor with an op amp. Am doing a 50Mhz crystal oscillator. Thanks.

  10. Great explanation and video. I have one nagging question regarding the circuit that I am hoping you can help me understand. At approximately 9:30 in the above video you explain the phase shifting components.
    The 180 degree output from the amplifier I understand.
    I understand 360 ( or in phase) signal is an oscillator requirement.
    I understand that when a signal is fed through a capacitor, a 90 degree shift occurs, but I am curious how capacitors C1 and C2 create a phase shift in the circuit when the signal fed through them goes to ground.
    Please help.
    Thanks for the great site!

  11. Hi Craig,
    Thanks for the video and gave me some insight.
    I am designing a pierce oscillator with discreet part, we ran out of the original integrated CMOS chip.
    It is for a 622MHZ MEMS oscillator.
    First, may I get your circuit tool to analyze the circuit.
    Second, I have some models for higher frequencies and need to modify for the right frequency. Do I use 2N2222 transistor?

    TIA,
    -Phil

  12. Hi Craig,
    I purchased a 6.5536 Mhz crystal and would like to see it produce oscillations on my oscilloscope. I watched your video and used your web tool to get some parameters for a circuit that I think might work. Now, I am not sure. On your web tool.. I have Vcc at 5V, R1=56k, R4=3.9K, 300 for the frequency, R3=1.5K, R2=27k, C1 and C2 = 182pf, C3=10-pf, C0=7pf, ESR=40, 2.5V peak to peak.. When all is said and done, I match my crystals load Capacitance at 12.01pf with a loaded Q=87.8 and a gain margin of 8.47. Those numbers look good. Crystal Drive Level is 0! My data sheet says I can go to a max of 1mw on crystal drive level. I am assuming that having this at 0, in my setup, is very efficient for producing oscillations. Is there a required Crystal Drive Level for operation and what can bump my values up if I need to increase it. Also, do I need to use a cap in the ampliffer section . you have that labelled as 0.1 on your web tool. Also, would my $400 Rigol oscilliscope be able to tell me the frequency? Thanks,Jeff

  13. If the top half of your circuit was replaced with a 74HCU04 inverter (which is apparently a typical set up for setting up a Pierce Oscillator for clocking a MCU), how would one go about calculating the various values your calculator uses? You’re not biasing a transistor into its linear region with that setup, so I’m a little fuzzy on the approach you’d take to do the math.

    • Yes, using an inverting CMOS gate is very common for Pierce oscillators. Take this circuit for example:

      Pierce gate oscillator

      Rf biases the inverter into its linear region. Its value is not terribly critical, typical values are 100k-1M (I usually use 1M).

      Rs is not strictly necessary, but it helps to isolate the feedback network from any reactive loads connected to the oscillator’s output, and reduces the drive level through the crystal, which aids in preventing heating in the crystal (this will probably not damage the crystal permanently, but will cause frequency drift on start up as the crystal warms up). I’ve found a value of 1k is usually a good starting point, but if your circuit doesn’t oscillate, you may need to reduce this value.

      The capacitors Ca and Cb are selected to provide the necessary capacitive load the crystal expects to see. This is specified in the crystal datasheet. Let’s say it’s 18pF; from the crystal’s point of view, those two capacitors are in series across the crystal terminals, so I might select 33pF for both capacitors. This gives a total capacitance of 16.5pF which is a bit low, but once you factor in the input capacitance of the inverter (I’m assuming ~2pF, but you should check the datasheet for your inverter IC) and maybe a couple pF of stray capacitance on the PCB, it gets you pretty close. Assuming 2pF of extra capacitance across both of those capacitors, you have a total capacitance of 35pF / 2, which works out to 17.5pF total. You may actually need to reduce the values used for the Ca and Cb capacitors, as the crystal itself will have some internal capacitance (usually specified as C0 in the crystal datasheet), which is typically 4-7pF. This capacitance will be effectively in parallel with the calculated 17.5pF external capacitance, which would make the total capacitance a bit high. Also note that there is no requirement that the Ca and Cb capacitors need to be equal value, although this is often done simply for convenience.

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